Design a high performance and low power radix-4 booth multiplier using power reduction techniques

Generally, to improve the multiplier’s performance radix-4 Booth algorithm is used decrease number of partial products (NOP) by half. Moreover, increased encoders as well decoders will subject more power usage. In this, a new kind pre-encoder design with reduced transistors proposed which could usage multiplier some extent and implement 16-bit for pre-encoders decoders. This helps reduce disabling all available from additional working. implemented using Cadence 45 nm technology. From simulation results, it seen that pre-encoded be able dynamic static 30% 41%, respectively, when compared traditional multiplier(16-bit). Compared previous mechanisms, has race-free characteristics consumes less power. contrast results approximate design, proves better also come up exact products.